This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 2005-71844, filed on Aug. 5, 2005, the contents of which are herein incorporated by reference in its entirety for all purposes.
1. Field of the Invention
The present invention relates, in general, to semiconductor memory devices and, more particularly, to a non-volatile semiconductor memory device, which has memory devices each capable of storing data in at least two charge trap regions depending on the direction of current flow, and a method of driving the non-volatile semiconductor memory device.
2. Description of the Related Art
Recently, a plurality of charge trap-type non-volatile memory devices using a charge storage layer that is made of a nonconducting material capable of locally storing charges, such as SiN, has been announced. Such charge trap-type non-volatile memory devices are advantageous compared to a floating gate-type non-volatile memory device using a floating gate because the manufacturing process is simplified in implementing high-density memory devices. A representative example of the charge trap-type non-volatile memory device is Nitride-storage Read Only Memory (NROM), as shown in FIG. 1. Referring to FIG. 1, NROM has thin film layers 13a, 13b and 13c, implemented with Oxide-Nitride-Oxide (ONO) films, as the insulating film layers of a gate 11 of a transistor.
In a charge trap-type non-volatile memory device, such as NROM, a data program operation is executed by injecting electrons, which are carriers, into the nitride film 13b, which is a charge storage layer. In other words, the charge trap-type non-volatile memory device performs the data program operation depending on variation in a threshold voltage caused by injected charges. Channel Hot-Electron injection (CHE) can be used as an electron injection method. Further, the erasure of data from the non-volatile memory device is performed by eliminating electrons injected into the nitride film 13b. In order to inject electrons, suitable voltages are applied to the gate node 11, first and second junction regions 15a and 15b, and the substrate 17 of the memory device, respectively.
For example, as shown in FIG. 2a, if a supply voltage VDD is applied to the first junction region 15a and a ground voltage VSS is applied to the second junction region 15b, the first junction region 15a acts as a drain D and the second junction region 15b acts as a source S. In this case, electrons are injected into the nitride film 13b near the first junction region 15a, that is, a charge trap region CT1, depending on the voltage level of the gate node 11. Consequently, the charge trap region CT1 is programmed by the increase of a threshold voltage.
Further, as shown in FIG. 2b, if the ground voltage VSS is applied to the first junction region 15a and the supply voltage VDD is applied to the second junction region 15b, the first junction region 15a acts as a source S and the second junction region 15b acts as a drain D. In this case, electrons are injected into the nitride film 13b near the second junction region 15b, that is, a charge trap region CT2, depending on the voltage level of the gate node 11. That is, the charge trap region CT2 is programmed by the increase of a threshold voltage.
Further, the reading of data stored in the charge trap regions CT1 and CT2 is performed by inversely controlling the direction of current flow used for programming. For example, as shown in FIG. 3a, if the supply voltage VDD is applied to the second junction region 15b, data stored in the charge trap region CT1 near the first junction region 15a is read as the voltage level of a bit line BL connected to the first junction region 15a depending on the voltage level of the gate node 11. That is, when the charge trap region CT1 is programmed, it is in a “turned off” state. In this case, the voltage level of the bit line BL is not adjusted to the supply voltage VDD, but is maintained at the ground voltage VSS. In contrast, when the charge trap region CT1 is not programmed, the voltage level of the bit line BL is adjusted to the supply voltage VDD.
Further, as shown in FIG. 3b, if the supply voltage VDD is applied to the first junction region 15a, data stored in the charge trap region CT2 near the second junction region 15b is read as the voltage level of a bit line BL connected to the second junction region 15b, depending on the voltage level of the gate node 11.
As described above, the non-volatile semiconductor memory device, such as NROM, can store data in two charge trap regions, so that it has a degree of integration twice that of a floating gate-type non-volatile semiconductor memory device.
Meanwhile, typical charge trap regions CT1 and CT2 map a bit of data depending on two threshold voltage levels. That is, as shown in FIG. 4, a bit of data is determined by a threshold voltage adjusted to one of two threshold voltage groups. For example, if the threshold voltage of the charge trap regions CT1 and CT2 is lower than a reference voltage VM, the voltage level of a corresponding bit line BL is adjusted to the supply voltage VDD and data “1” is read at the time of reading data. Further, if the threshold voltage of the charge trap regions CT1 and CT2 is higher than the reference voltage VM, the voltage level of a corresponding bit line BL is adjusted to the ground voltage VSS and data “0” is read at the time of reading data.
However, with the high degree of integration of a non-volatile semiconductor memory device, a charge trap-type non-volatile semiconductor memory device having a higher degree of integration is required. That is, a non-volatile semiconductor memory device including two charge trap regions CT1 and CT2, each storing a data value having two or more bits, is required.